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integrated silicon solution, inc. ? 1-800-379-4774 1 rev. a 05/13/05 issi ? is43r83200a -6,-75 (4-bank x 8,388,608 - word x 8-bit) is43r16160a -6,-75 (4-bank x 4,194,304 - word x 16-bit) 256 mb ddr synchronous dram description is43r83200a is a 4-bank x 8,388,608-word x 8bit, is43r16160a is a 4-bank x 4,194,304-word x 16bit double data rate synchronous dram, with sstl_2 interface. all control and address signals are referenced to the rising edge of clk. - vdd=vddq=2.5v 0.2v power supply for -6,-75. - double data rate architecture ; two data transfers per clock cycle. - bidirectional, data strob (dqs) is transmitted/received with data - differential clock input (clk and /clk) - dll aligns dq and dqs transitions with clk transitions edges of dqs - commands entered on each positive clk edge ; - data and data mask referenced to both edges of dqs - 4 bank operation controlled by ba0 , ba1 (bank address) - /cas latency - 2.0 / 2.5/ 3 (programmable) ; burst length - 2 / 4 / 8 (programmable) burst type - sequential / interleave (programmable) - auto precharge / all bank precharge controlled by a10 - 8192 refresh cycles / 64ms (4 banks concurrent refresh) - auto refresh and self refresh - row address a0-12 / column address a0-9(x8) /a0-8(x16) - sstl_2 interface - package 400-mil, 66-pin thin small outline package (tsop ii) with 0.65mm lead pitch - jedec standard for -6 , -75 - lead-free available features input data is registered on both edges of data strob , and output data and data strobe are referenced on both edges of clk. the is43r83200a/16160a achieves high speed clock rate up to 166 mhz .
2 integrated silicon solution, inc. ? 1-800-379-4774 rev. a 05/13/05 issi ? is43r83200a -6,-75 (4-bank x 8,388,608 - word x 8-bit) is43r16160a -6,-75 (4-bank x 4,194,304 - word x 16-bit) pin configura tion (t op view) pin configuration (top view) vdd dq0 vddq nc dq1 vssq nc dq2 vddq nc dq3 vssq nc nc vddq nc nc vdd nc nc / we /cas /ras /cs nc ba0 ba1 a10/ap a0 a1 a2 a3 vdd vss dq7 vssq nc dq6 vddq nc dq5 vssq nc dq4 vddq nc nc vssq dqs nc vref vss dm / clk clk cke nc a12 a11 a9 a8 a7 a6 a5 a4 vss x8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 66pin tsop(ii) 400milx875mil (0.65mm lead pitch) x16 vdd dq0 vddq dq1 dq2 vssq dq3 dq4 vddq dq5 dq6 vssq dq7 nc vddq ldqs nc vdd nc ldm / we /cas /ras /cs nc ba0 ba1 a10/ap a0 a1 a2 a3 vdd vss dq15 vssq dq14 dq13 vddq dq12 dq11 vssq dq10 dq9 vddq dq8 nc vssq udqs nc vref vss udm / clk clk cke nc a12 a11 a9 a8 a7 a6 a5 a4 vss c l k ,/c l k : master clock a0 - 1 2 : address input ck e : clock enable ba0 , 1 : bank address input / cs : chip select vd d : power supply / ras : row address strobe vd d q : power supply for outpu t / ca s : column address strobe vs s : ground / we : write enable vs s q : ground for output dq 0 - 7 : data i/o dq s : data strobe dm : wrtie mask vr e f : reference voltage
integrated silicon solution, inc. ? 1-800-379-4774 3 rev. a 05/13/05 issi ? is43r83200a -6,-75 (4-bank x 8,388,608 - word x 8-bit) is43r16160a -6,-75 (4-bank x 4,194,304 - word x 16-bit) block diagram
mode register control circuitry address buffer clock buffer control signal buffer clk, /clk cke a0-12 ba0,1 /cs dll i/o buffer dqs dq0-7 qs buffer dm /we /cas /ras memory array bank#0 memory array bank#1 memory array bank#2 memory array bank#3 note: this figure shows the is4 3r83200 a. the is4 3r16160 a configuration is 8192x512x16 of cell array and dq0-15
4 integrated silicon solution, inc. ? 1-800-379-4774 rev. a 05/13/05 issi ? is43r83200a -6,-75 (4-bank x 8,388,608 - word x 8-bit) is43r16160a -6,-75 (4-bank x 4,194,304 - word x 16-bit) pin function
symbol type description clk,/clk input clock: clk and /clk are differential clock inputs. all address and control input signals are sampled on the crossing of the positive edge of clk and negative edge of /clk. output (read) data is referenced to the crossings of clk and /clk (both directions of crossing). cke input clock enable: cke controls internal clock. when cke is low, internal clock for the following cycle is ceased. cke is also used to select auto / self refresh. after self refresh mode is started, cke becomes asynchronous input. self refresh is maintained as long as cke is low. /cs input chip select: when /cs is high, any command means no operation. /ras, /cas, /we input combination of /ras, /cas, /we defines basic commands. a0-12 input a0-12 specify the row / column address in conjunction with ba0,1. the row address is specified by a0-12. the column address is specified by a0-9(x8) and a0-8(x16). a10 is also used to indicate precharge option. when a10 is high at a read / write command, an auto precharge is performed. when a10 is high at a precharge command, all banks are precharged. ba0,1 input bank address: ba0,1 specifies one of four banks to which a command is applied. ba0,1 must be set with act, pre, read, write commands. dq0-15(x16) dq0-7(x8), input / output data input/output: data bus ldqs, udqs (x16) dqs (x8) input / output data strobe: output with read data, input with write data. edge-aligned with read data , centered in write data. used to capture write data. ldm, udm (x16) dm (x8) input input data mask: dm is an input mask signal for write masked when dm is sampled high along with that input data during a write access. dm is sampled on both edges of dqs. although dm pins are input only, the dm loading matches the dq and dqs loading. vdd, vss power suppl y power supply for the memory array and peripheral circuitry. vddq, vssq power suppl y vddq and vssq are supplied to the output buffers only. vref input sstl_2 reference voltage.
integrated silicon solution, inc. ? 1-800-379-4774 5 rev. a 05/13/05 issi ? is43r83200a -6,-75 (4-bank x 8,388,608 - word x 8-bit) is43r16160a -6,-75 (4-bank x 4,194,304 - word x 16-bit) basic functions
the is4 3r83200 a/16160a provides basic
functions, bank (row) activate, burst read / write,
bank (row) precharge, and auto / self refresh.
each command is defined by control signals of /
ras, /cas and /we at clk rising edge.
in addition to 3 signals, /cs ,cke and a10 are
/clk clk used as chip select,refresh option , and precharge
option , respectively .
to know the detailed definition of commands, please
see the command truth table.
/cs chip select : l=select, h=deselect /ras command /cas command define basic commands /we command cke refresh option @refresh command a10 precharge option @precharge or read/write command activate (act) [/ras =l, /cas =/we =h] act command activates a row in an idle bank indicated by ba. read (read) [/ras =h, /cas =l, /we =h] read command starts burst read from the active bank indicated by ba. first output data appears after /cas latency. when a10 =h at this command, the bank is deactivated after the burst read (auto-precharge, reada ). write (write) [/ras =h, /cas =/we =l] write command starts burst write to the active bank indicated by ba. total data length to be written is set by burst length. when a10 =h at this command, the bank is deactivated after the burst write (auto-precharge, writea ). precharge (pre) [/ras =l, /cas =h, /we =l] pre command deactivates the active bank indicated by ba. this command also terminates burst read / write operation. when a10 =h at this command, all banks are deactivated (precharge all, prea ). auto-refresh (refa) [/ras =/cas =l, /we =cke =h] refa command starts auto-refresh cycle. refresh address including bank address are generated internally. after this command, the banks are precharged automatically.
6 integrated silicon solution, inc. ? 1-800-379-4774 rev. a 05/13/05 issi ? is43r83200a -6,-75 (4-bank x 8,388,608 - word x 8-bit) is43r16160a -6,-75 (4-bank x 4,194,304 - word x 16-bit) command truth t able
command mnemonic cke n-1 cke n /cs /ras /cas /we ba0,1 a10 /ap a0-9, 11-12 note deselect desel h h h x x x x x x no operation nop h h l h h h x x x row address entry & bank activate act h h l l h h v v v sin gle bank precharge pre h h l l h l v l x precharge all banks prea h h l l h l x h x column address entry & write write h h l h l l v l v column address entry & write with a uto-precharge writea h h l h l l v h v column address entry & read read h h l h l h v l v column address entry & read with a uto-precharge reada h h l h l h v h v auto-refresh refa h h l l l h x x x self-refresh entr y refs h l l l l h x x x self-refresh exit refsx l h h x x x x x x l h l h h h x x x burst terminate term h h l h h l x x x 1 mode re gister set mrs h h l l l l l l v 2 h=high level, l=low level, v=valid, x=don't care, n=clk c ycle number note: 1. applies only to read bursts with autoprecharge disabled; this command is undefined (and should not be used) for read bursts with autoprecharge enabled, and for write bursts. 2. ba0-ba1 select either the base or the extended mode register (ba0 = 0, ba1 = 0 selects mode register; ba0 = 1, ba1 = 0 selects extended mode register; other combinations of ba0-ba1 are reserved; a0-a11 provide the op- code to be written to the selected mode register.
integrated silicon solution, inc. ? 1-800-379-4774 7 rev. a 05/13/05 issi ? is43r83200a -6,-75 (4-bank x 8,388,608 - word x 8-bit) is43r16160a -6,-75 (4-bank x 4,194,304 - word x 16-bit) function truth t able
current state /cs /ras /cas /we address command action notes idle h x x x x desel nop l h h h x nop nop l h h l ba term illegal 2 l h l x ba, ca, a10 read / write illegal 2 l l h h ba, ra act bank active, latch ra l l h l ba, a10 pre / prea nop 4 l l l h x refa auto-refresh 5 l l l l op-code, mode-add mrs mode re gister set 5 row active h x x x x desel nop l h h h x nop nop l h h l ba term nop l h l h ba, ca, a10 read / reada be gin read, latch ca, determine auto-prechar ge l h l l ba, ca, a10 write / writea be gin write, latch ca, determine auto-prechar ge l l h h ba, ra act bank active / illegal 2 l l h l ba, a10 pre / prea precharge / precharge all l l l h x refa illegal l l l l op-code, mode-add mrs illegal read (auto- precharge disabled) h x x x x desel nop (continue burst to end ) l h h h x nop nop (continue burst to end ) l h h l ba term terminate burst l h l h ba, ca, a10 read / reada terminate burst, latch ca, be gin new read, determine auto-prechar ge 3 l h l l ba, ca, a10 write writea illegal l l h h ba, ra act bank active / illegal 2 l l h l ba, a10 pre / prea terminate burst, prechar ge l l l h x refa illegal l l l l op-code, mode-add mrs illegal
8 integrated silicon solution, inc. ? 1-800-379-4774 rev. a 05/13/05 issi ? is43r83200a -6,-75 (4-bank x 8,388,608 - word x 8-bit) is43r16160a -6,-75 (4-bank x 4,194,304 - word x 16-bit) function truth t able (continued) current state /cs /ras /cas /we address command action notes write (auto- precharge disabled) h x x x x desel nop (continue burst to end ) l h h h x nop nop (continue burst to end ) l h h l ba term illegal l h l h ba, ca, a10 read / reada terminate burst, latch ca, be gin read, determine auto- precharge 3 l h l l ba, ca, a10 write / writea terminate burst, latch ca, be gin write, determine auto- precharge 3 l l h h ba, ra act bank active / illegal 2 l l h l ba, a10 pre / prea terminate burst, prechar ge l l l h x refa illegal l l l l op-code, mode-add mrs illegal read with auto precharge h x x x x desel nop (continue burst to end ) l h h h x nop nop (continue burst to end ) l h h l ba term illegal l h l h ba, ca, a10 read / reada illegal l h l l ba, ca, a10 write / writea illegal l l h h ba, ra act bank active / illegal 2 l l h l ba, a10 pre / prea precharge/illegal 2 l l l h x refa illegal l l l l op-code, mode-add mrs illegal write with auto precharge h x x x x desel nop (continue burst to end ) l h h h x nop nop (continue burst to end ) l h h l ba term illegal l h l h ba, ca, a10 read / reada illegal l h l l ba, ca, a10 write / writea illegal l l h h ba, ra act bank active / illegal 2 l l h l ba, a10 pre / prea precharge/illegal 2 l l l h x refa illegal l l l l op-code, mode-add mrs illegal
integrated silicon solution, inc. ? 1-800-379-4774 9 rev. a 05/13/05 issi ? is43r83200a -6,-75 (4-bank x 8,388,608 - word x 8-bit) is43r16160a -6,-75 (4-bank x 4,194,304 - word x 16-bit) function truth t able (continued) current state / cs / ras / cas / we address command action pre - charging h x x x x desel nop ( idle after trp ) l h h h x nop nop ( idle after trp ) l h h l ba term illegal l h l x ba, ca, a10 read / write illegal l l h h ba, ra act illegal l l h l ba, a10 pre / prea nop ( idle after trp ) l l l h x refa illegal l l op-code, mode-add mrs illegal row activating h x x x x desel nop ( row active after trcd ) l h h h x nop nop ( row active after trcd ) l h h l ba term illegal l h l x ba, ca, a10 read / write illegal l l h h ba, ra act illegal l l h l ba, a10 pre / prea illegal l l l h x refa illegal l l op-code, mode-add mrs illegal write re- covering h x x x x desel nop l h h h x nop nop l h h l ba term illegal l h l x ba, ca, a10 read / write illegal l l h h ba, ra act illegal l l h l ba, a10 pre / prea illegal l l l h x refa illegal l l op-code, mode-add mrs illegal note s 2 2 2 4 2 2 2 2 2 2 2 2 l l l l l l
10 integrated silicon solution, inc. ? 1-800-379-4774 rev. a 05/13/05 issi ? is43r83200a -6,-75 (4-bank x 8,388,608 - word x 8-bit) is43r16160a -6,-75 (4-bank x 4,194,304 - word x 16-bit) function truth t able (continued) current state /cs /ras /cas /we address command action notes re- freshing h x x x x desel nop (idle after trc) l h h h x nop nop (idle after trc) l h h l ba term illegal l h l x ba, ca, a10 read / write illegal l l h h ba, ra act illegal l l h l ba, a10 pre / prea illegal l l l h x refa illegal l l l l op-code, mode-add mrs illegal mode register setting h x x x x desel nop (idle after trsc ) l h h h x nop nop (idle after trsc) l h h l ba term illegal l h l x ba, ca, a10 read / write illegal l l h h ba, ra act illegal l l h l ba, a10 pre / prea illegal l l l h x refa illegal l l l l op-code, mode-add mrs illegal a bbreviations:
h=hi gh level, l=low level, x=don't care
ba=bank address, ra=row address, ca=column address, nop=no o peration
notes: 1. all entries assume that cke was hi gh during the preceding clock cycle and the current clock cycle. 2. illegal to bank in s pecified state; function ma y be le gal in the bank indicated by ba, depending on the state of that bank. 3. must satisf y bus contention, bus turn around, write recovery requirements. 4. nop to bank precharging or in idle state. may precharge bank indicated by ba. 5. illegal if any bank is not idle. illegal = device o peration and/or data-inte grity are not guaranteed.
integrated silicon solution, inc. ? 1-800-379-4774 11 rev. a 05/13/05 issi ? is43r83200a -6,-75 (4-bank x 8,388,608 - word x 8-bit) is43r16160a -6,-75 (4-bank x 4,194,304 - word x 16-bit) function truth t able (continued) current state cke n-1 cke n / cs / ras / cas / we add action self- refresh h x x x x x x invalid l h h x x x x exit self-refresh ( idle after trc ) l h l h h h x exit self-refresh ( idle after trc ) l h l h h l x illegal l h l h l x x illegal l h l l x x x illegal l l x x x x x nop ( maintain self-refresh ) power down h x x x x x x invalid l h x x x x x exit power down to idle l l x x x x x nop ( maintain self-refresh ) all banks idle h h x x x x x refer to function truth table h l l l l h x enter self-refresh h l h x x x x enter power down h l l h h h x enter power down h l l h h l x illegal h l l h l x x illegal h l l l x x x illegal l x x x x x x refer to current state =power down any state other than listed above h h x x x x x refer to function truth table h x x x x x be g in clk suspend at next c y cle l h x x x x x exit clk suspend at next c y cle l l x x x x x maintain clk suspend notes 3 3 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 l abbreviations:
h=hi gh level, l=low level, x=don't care
notes:
1.cke low to high transition will re-enable clk and other inputs asynchronously.
a minimum setup time must be satisfied before any command other than exit. 2.power-down and self-refresh can be entered only from the all banks idel state. 3.must be legal command.
12 integrated silicon solution, inc. ? 1-800-379-4774 rev. a 05/13/05 issi ? is43r83200a -6,-75 (4-bank x 8,388,608 - word x 8-bit) is43r16160a -6,-75 (4-bank x 4,194,304 - word x 16-bit) simplified state diagram p o w e r a p p l i e d r o w a c t i v e i d l e p r e c h a r g e p o w e r d o w n r e a d a w r i t e a p o w e r o n a c t r e f a r e f s r e f s x c k e l c k e h m r s c k e l c k e h w r i t e r e a d w r i t e a w r i t e a r e a d a r e a d p r e r e a d a r e a d a p r e p r e p r e a m o d e r e g i s t e r s e t s e l f r e f r e s h a u t o r e f r e s h a c t i v e p o w e r d o w n a u t o m a t i c s e q u e n c e w r i t e r e a d p r e c h a r g e a l l m r s b u r s t s t o p t e r m r e a d w r i t e c o m m a n d s e q u e n c e
integrated silicon solution, inc. ? 1-800-379-4774 13 rev. a 05/13/05 issi ? is43r83200a -6,-75 (4-bank x 8,388,608 - word x 8-bit) is43r16160a -6,-75 (4-bank x 4,194,304 - word x 16-bit) mode register burst length , burst type and /cas latency can
be programmed by setting the mode register
(mrs).the mode register stores there data until
the next mrs command , which may be issued
when both banks are in idel state.
after trsc from a mrs command , the ddr
sdram is ready for new command.
clk /clk /cs /ras /cas r: reserved for future use bl 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 burst len g th bt= 0 bt= 1 r 2 4 8 r r r r r 2 4 8 r r r r 0 1 burst t y pe se q uential interleaved a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 ba1 ba0 0 0 dr 0 ltmode bt bl 0 0 0 / we a11-a0 ba0 ba1 cl latency mode / cas latenc y r r 2 3 r r 2.5 r 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 1 dll reset no yes a12 0 power on sequence before starting normal operation , the following
power on sequence is nessary to prevent a
sdram from damaged or multifunctioning.
1.apply vdd before or the same time as vddq
2.apply vddq before or at the same time as vtt &
vref.
3.maintain stable condition for 200us after stable
power and clk , apply nop or dsel.
4.issue precharge command for all banks of the
device.
5.issue emrs
6.issue mrs
7.issue 2 or more auto refresh commands
8.maintain stable condition for 200 cycle
after these sequence , the sdram is idle state and
ready for normal operation.
v
14 integrated silicon solution, inc. ? 1-800-379-4774 rev. a 05/13/05 issi ? is43r83200a -6,-75 (4-bank x 8,388,608 - word x 8-bit) is43r16160a -6,-75 (4-bank x 4,194,304 - word x 16-bit) extended mode register dll disable / enable mode can be programmed
by setting the extended register (emrs).
the extended mode register stores these data until
the next emrs command , which may be issued
when all banks are in idle state.
after trsc from a emrs command is readly for
new command.
clk /clk /cs /ras /cas /we a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 ba1 ba0 a12 ba0 a11-a0 ba1 0 0 0 dd 1 0 0 ds 0 0 0 0 0 0 0 v dll disable 0 dll enable 1 dll disable drive stren gth 0 normal 1 weak
integrated silicon solution, inc. ? 1-800-379-4774 15 rev. a 05/13/05 issi ? is43r83200a -6,-75 (4-bank x 8,388,608 - word x 8-bit) is43r16160a -6,-75 (4-bank x 4,194,304 - word x 16-bit) /clk clk command address dqs dq burst len g th burst len g th y read write q0 q1 q2 q3 d0 d1 d2 d3 y cl= 2 /cas latenc y bl= 4 a2 a1 a0 initial address bl se q uential interleaved column addressin g 0 0 0 0 1 1 1 1 - 0 - 1 - 0 - 1 - 0 2 6 1 5 1 3 7 0 4 2 4 0 3 7 3 5 1 2 6 4 6 2 5 1 5 7 3 4 0 6 0 4 7 3 7 1 0 2 1 3 2 0 3 0 7 6 0 1 1 0 2 3 3 0 - 1 1 3 5 3 2 1 1 8 4 2 0 0 1 0 0 1 1 1 0 0 1 0 0 1 1 1 0 0 1 1 0 - 1 5 4 3 0 7 4 3 2 7 6 2 6 5 4 1 0 5 2 3 6 7 3 7 6 5 2 1 6 1 0 5 4 4 0 7 6 3 2 7 0 1 4 5 5 1 0 7 4 3 0 7 6 3 2 6 2 1 0 5 4 1 6 7 2 3 7 3 2 1 6 5 2 5 4 1 0 0 2 1 3 2 0 3 1 0 1 4 5 3 2 2 3 1 0 2 1 1 - 2 0 4 6 0 1 0 0
16 integrated silicon solution, inc. ? 1-800-379-4774 rev. a 05/13/05 issi ? is43r83200a -6,-75 (4-bank x 8,388,608 - word x 8-bit) is43r16160a -6,-75 (4-bank x 4,194,304 - word x 16-bit) opera tion al description bank active the ddr sdram has four independent
banks.
each bank address (ba0,1). a row is
indicated by the row address a12-0.
the minimum activation interval between
one bank and the other bank is trrd.
maximum 2 act commands are allowed
within trc ,
although the number of banks which are
active concurrently is not limited.
precharge the ddr sdram has four independent
banks.
each bank address (ba0,1). a row is
indicated by the row address a12-0.
the minimum activation interval between
one bank and the other bank is trrd.
maximum 2 act commands are allowed
within trc ,
although the number of banks which are
active concurrently is not limited.
ba n k a c ti vat i o n an d pr ech ar g e a l l (bl = 8 , c l = 2 ) /clk clk command a0-9,11-12 a10 ba0,1 dqs
dq
act xa xa 00 read y 0 00 act xb xb 01 pre trrd trcd 1 act xb xb 01 tras trp trcmin 2 act command / trcmin qa0 bl/2 qa1 qa2 qa3 qa4 qa5 qa6 qa7 precharge all a precharge command can be issued at bl/2 from a read command without data loss.
integrated silicon solution, inc. ? 1-800-379-4774 17 rev. a 05/13/05 issi ? is43r83200a -6,-75 (4-bank x 8,388,608 - word x 8-bit) is43r16160a -6,-75 (4-bank x 4,194,304 - word x 16-bit) read after trcd from the bank activation, a read command can be issued. 1st output data is avail- able after the /cas latency from the read, followed by (bl -1) consecutive data when the burst length is bl. the start address is specified by a9-0(x8)/a8-0(x16) , and the address sequence of burst data is defined by the burst t ype. a read command may be applied to any active bank, so the row precharge time (trp) can be hidden behind continuous output data by interleaving the multiple banks. when a10 is high at a read command, the auto-precharge (reada) is performed. any command (read, write, pre , act) to the same bank is inhibited till the internal precharge is complete. the internal precharge starts at bl/2 after reada. the next act command can be issued after (bl/2 + trp) from the previous reada. /clk clk command a0-9,11-12 a10 ba0,1 dqs dq mu lt i ban ki nt er leav in gr ead (bl=8, cl =2 ) act xa xa 00 read y 0 00 read y 0 10 act xb xb 10 pre 0 00 trcd /cas latency burst length qa0 qa1 qa2 qa3 qa4 qa5 qa6 qa7 qb0 qb1 qb2 qb3 qb4 qb5 qb7 qb8
18 integrated silicon solution, inc. ? 1-800-379-4774 rev. a 05/13/05 issi ? is43r83200a -6,-75 (4-bank x 8,388,608 - word x 8-bit) is43r16160a -6,-75 (4-bank x 4,194,304 - word x 16-bit) re a d au to -pr ech ar g e t i mi n g (b l = 8) /clk clk command cl=2.5 dq cl=2 dq cl=1.5 dq act read bl/2 qa0 qa0 qa0 qa1 qa2 qa3 qa4 qa5 qa6 qa7 qa1 qa2 qa3 qa4 qa5 qa6 qa7 qa1 qa2 qa3 qa4 qa5 qa6 qa7 internal precharge start timing re ad wi th au to-pr ec harg e( bl =8 ,c l= 2) /clk clk act xa xa 00 read y 1 00 act xb xb 00 trcd trp bl/2 + trp bl/2 qa0 qa1 qa2 qa3 qa4 qa5 qa6 qa7 command a0-9,11-12 a10 ba0,1 dqs dq internal precharge start
integrated silicon solution, inc. ? 1-800-379-4774 19 rev. a 05/13/05 issi ? is43r83200a -6,-75 (4-bank x 8,388,608 - word x 8-bit) is43r16160a -6,-75 (4-bank x 4,194,304 - word x 16-bit) write after trcd from the bank activation , a write command can be issued. 1st input data is set at the same cycle as the write. following (bl -1) data are written into the ram, when the burst length is bl. the start address is specified by a9-0(x8)/a8-0(x16) and the address sequence of burst data is defined by the burst type. a write command may be applied to any active bank, so the row precharge time (trp) can be hidden behind continuous input data by interleaving the multiple banks. from the last input data to the pre command, the write recovery time (twr) is required. when a10 is high at a write command, the autoprecharge (writea) is performed. any command (read, write, pre, tbst, act) to the same bank is inhibited till the internal precharge is complete. the internal precharge begins at twr after the last input data cycle. (need to keep tras min.) the next act command can be issued after trp from the internal precharge timing. mu l ti ban k i n te r l eav i n g w ri t e (b l = 8 ) /clk clk command a0-9,11-12 a10 ba0,1 dqs dq act 00 write 00 write 0 0 10 act xb 10 0 10 trcd trcd pre xa 0 00 pre da0 da1 da2 da3 da4 da5 da6 da7 db0 db1 db2 db3 db4 db5 db6 db7 xa ya yb xb w r i t e w it h a u to- pr e c h a r ge (b l= 8 ) /clk clk command a0-9,11-12 a10 ba0,1 dqs dq act xa 00 write 1 00 act xb 00 trc d da0 da1 da2 da3 da4 da5 da6 da7 tdal xa y xb
20 integrated silicon solution, inc. ? 1-800-379-4774 rev. a 05/13/05 issi ? is43r83200a -6,-75 (4-bank x 8,388,608 - word x 8-bit) is43r16160a -6,-75 (4-bank x 4,194,304 - word x 16-bit) burst interruption [ read interrupted by read ] burst read operation can be interrupted by new read of any bank. random column access is allowed. read to read interval is minimum 1 clk.. [ read interrupted by precharge] burst read operation can be interrupted by precharge of the same bank. read to pre interval is minimum 1 clk. a pre command to output disable latency is equivalent to the /cas latency. as a result , read to pre interval determines valid data length to be output. the figure below shows examples of bl=8. rea d i n te rru p ted b y pr e c h arg e (bl = 8 ) /clk clk command dqs dq command cl=2.5 dqs dq command q0 q1 q2 q3 q0 q1 q0 q1 q2 q3 q4 q5 pre read read pre read pre dqs dq rea di nt e rru pt ed by re ad (b l= 8, cl =2 ) /clk clk command a0-9,11 a10 ba0,1 dqs dq yi read read read read yj yk yl 00 00 10 00 01 qai0 qai1 qaj0 qaj1 qaj2 qaj3 qak0 qak1 qak2 qak3 qak4 qak5 qal0 qal1 qal2 qal3 qal4 qal5 qal6 qal7 00
integrated silicon solution, inc. ? 1-800-379-4774 21 rev. a 05/13/05 issi ? is43r83200a -6,-75 (4-bank x 8,388,608 - word x 8-bit) is43r16160a -6,-75 (4-bank x 4,194,304 - word x 16-bit) cl=2.0
/clk clk command dqs dq command dqs dq command dqs dq rea d inte rru pt ed by prech arg e ( bl =8) q0 q1 q2 q3 q0 q1 q0 q1 q2 q3 q4 q5 pre read read pre read pre
22 integrated silicon solution, inc. ? 1-800-379-4774 rev. a 05/13/05 issi ? is43r83200a -6,-75 (4-bank x 8,388,608 - word x 8-bit) is43r16160a -6,-75 (4-bank x 4,194,304 - word x 16-bit) [read interrupted by burst stop] burst read operation can be interrupted by a burst stop command(term) .
read to term interval is minimum 1 clk . a term command to output disable latency is equivalent to
the /cas latency.
as a result , read to term interval determines valid data length to be output .
the figure below shows examples of bl=8.
rea d i n te rru p ted b y t erm (b l = 8) /clk clk command dqs dq command q0 q1 q2 q3 q0 q1 q0 q1 q2 q3 q4 q5 term read read term read term q0 q1 q2 q3 q0 q1 q0 q1 q2 q3 q4 q5 term read read term read term cl=2.5
dqs dq command dqs dq command dqs dq command cl=2.0
dqs dq command dqs dq
integrated silicon solution, inc. ? 1-800-379-4774 23 rev. a 05/13/05 issi ? is43r83200a -6,-75 (4-bank x 8,388,608 - word x 8-bit) is43r16160a -6,-75 (4-bank x 4,194,304 - word x 16-bit) [read interrupted by write with term] rea d i n te rru p ted b y t erm (b l = 8) /clk
clk
q0 q1 q2 q3 read term write d0 d1 d2 d3 d4 d5 q0 q1 q2 q3 read term write d0 d1 d2 d3 d4 d5 d6 d7 cl=2.5
cl=2.0
command dqs
dq
command dqs
dq

24 integrated silicon solution, inc. ? 1-800-379-4774 rev. a 05/13/05 issi ? is43r83200a -6,-75 (4-bank x 8,388,608 - word x 8-bit) is43r16160a -6,-75 (4-bank x 4,194,304 - word x 16-bit) [ write interrupted by write] burst write operation can be interrupted by write of any write to write interval is minimum 1 clk. bank.random column access is allowed . [write interrupted by read] burst write operation can be interrupted by read of the same or the other bank. random column
access is allowed. internal write to read command interval(twtr) is minimum 1 clk . the input
data on dq at the interrupting read cycle is dont care.
twtr is referenced from the first positive edge after the last data input.
w r i te i n ter ru p te d b y rea d (bl = 8 , c l = 2. 5) /clk clk command a0-9,11-12 a10 ba0,1 dm qs dq write yi 0 00 read yj 0 00 dai0 dai1 qaj0 qaj1 qaj2 qaj3 qaj4 qaj5 qaj6 qaj7 twtr /clk clk command a0-9,11 a10 ba0,1 dqs dq wr it ei nt er ru pt ed by wr it e( bl =8 ) write yi 0 00 write yk 0 10 write yj 0 00 write yl 0 00 dai1 daj1 daj3 dak1 dak3 dak5 dal1 dal2 dal 3 dal 5 dal 6 dal 7 dal 4 dal 0 dak4 dak2 dak0 dai 0 daj 0 daj2
integrated silicon solution, inc. ? 1-800-379-4774 25 rev. a 05/13/05 issi ? is43r83200a -6,-75 (4-bank x 8,388,608 - word x 8-bit) is43r16160a -6,-75 (4-bank x 4,194,304 - word x 16-bit) [write interrupted by precharge] burst write operation can be interrupted by precharge of the same or all bank . random column access is allowed. twr is referenced from the first positive clk edge after the last data input. write int erru pted by p rec ha rg e ( bl =8, cl=2.5) /clk
clk
command a0-9,11-12 a10 ba0,1 dm
qs
dq
write yi 0 00 pre 00 dai0 dai1 twr
26 integrated silicon solution, inc. ? 1-800-379-4774 rev. a 05/13/05 issi ? is43r83200a -6,-75 (4-bank x 8,388,608 - word x 8-bit) is43r16160a -6,-75 (4-bank x 4,194,304 - word x 16-bit) [auto refresh] single cycle of auto-refresh is initiated with a refa(/cs=/ras=/cas=l , /we=cke=h) command. the refresh address is generated internally . 8192 refa cycles within 64ms refresh 256mbits memory cells. the auto-refresh is performed on 4 banks concurrently. before performing an auto-refresh , all banks must be in the idel state. auto-refresh to auto-refresh interval is minimum trfc. any command must not be supplied to the device before trfc from the refa command. a uto-refresh /clk clk /cs /ras /cas /we cke nop or deselect trfc a0-12 ba0,1 auto refresh on all banks auto refresh on all banks [i n i ti al i z e an d m od e r e gi s te r s e ts ] /clk clk emrs pre nop mrs pre ar ar mrs act code code xa code xa 1 0 xa code 1 1 00 00 code tmrd tmrd trp trfc trfc tmrd cke command a0-9,11,12 a10 ba0,1 dqs dq extended mode register set mode register set reset dll
integrated silicon solution, inc. ? 1-800-379-4774 27 rev. a 05/13/05 issi ? is43r83200a -6,-75 (4-bank x 8,388,608 - word x 8-bit) is43r16160a -6,-75 (4-bank x 4,194,304 - word x 16-bit) [self refresh] self-refresh mode is entered by issuing a refs command (/cs=/ras=/cas=l , /we=h , cke=l).
once the self-refresh is initiated , it is maintained as long as cke is kept low. during the self-refresh mode ,
cke is asynchronous and the only enable input , all other input including clk are disable and ignored , so
that power consumption due to synchronous input is saved. to exit the self-refresh , supplying stable clk
input , asserting desel or nop command and then asserting cke for longer than txsnr/txsrd.
self-refresh /clk clk /cs /ras /cas /we txsnr x x txsrd y y cke a0-12 ba0,1 self refresh exit
28 integrated silicon solution, inc. ? 1-800-379-4774 rev. a 05/13/05 issi ? is43r83200a -6,-75 (4-bank x 8,388,608 - word x 8-bit) is43r16160a -6,-75 (4-bank x 4,194,304 - word x 16-bit) [asynchronous self refresh] asynchronous self-refresh mode is entered by cke=l within 2 tclk after issuing a refa command
(/cs=/ras=/cas=l , /we=h).
once the self-refres is initiated , it is maintained as long as cke is kept low. during the self-refresh
mode , cke is asynchronous and the only enable input , all other inputs including clk are disable and
ignored , so that power consumption due to synchronous input is saved. to exit the self-refresh ,
supplying stable clk inputs , asserting desel or nop command and then asserting cke for longer
than txsnr/txsrd.
asynchr onous self-refresh /clk clk /cs /ras /cas /we cke txsnr max 2 tclk a0-12 ba0,1 self refresh exit
integrated silicon solution, inc. ? 1-800-379-4774 29 rev. a 05/13/05 issi ? is43r83200a -6,-75 (4-bank x 8,388,608 - word x 8-bit) is43r16160a -6,-75 (4-bank x 4,194,304 - word x 16-bit) [power down] the purpose of clk suspend is power down . cke is synchronous input except during the self-refresh mode . a command at cycle is ignored . from cke=h to normal function , dll recovery time is not required in the condition of the stable clk operation during the power down mode. p o wer do wn b y cke / clk clk cke command cke command pre act standb y power down active power down nop nop valid nop nop valid txpnr/ txprd [dm control] dm is defined as the data mask for writes . during writes , dm masks input data word . dm to write mask latency is 0 . dm function(bl=8 , cl=2) /clk clk command dm dqs dq write read d0 d1 d3 d4 d5 d6 d7 don't care q2 q3 q4 q5 q0 q1 q6 masked by dm=h
30 integrated silicon solution, inc. ? 1-800-379-4774 rev. a 05/13/05 issi ? is43r83200a -6,-75 (4-bank x 8,388,608 - word x 8-bit) is43r16160a -6,-75 (4-bank x 4,194,304 - word x 16-bit) tis tih vref valid data read operation tac tdqsck tcl tch tck tdqsq tqh trpre trpst tqpre tqpst c md & / clk
clk
add. dqs
/qfc
dq
write operation / tdqss=max. /clk
clk
dqs
/qfc
tdqss tds tdh tdqsl tdqsh twpre tdss twpres twpst tqck tqoh ( min ) dq write operation / tdqss=min. /clk clk dqs /qfc tdqss tds tdh tdqsl tdqsh twpre tdsh twpres twpst tqck tqoh ( max ) dq

integrated silicon solution, inc. ? 1-800-379-4774 31 rev. a 05/13/05 issi ? is43r83200a -6,-75 (4-bank x 8,388,608 - word x 8-bit) is43r16160a -6,-75 (4-bank x 4,194,304 - word x 16-bit) absolute maximum ra tings
s y mbol parameter conditions ratin g s unit vdd suppl y volta g e with respect to vss -0.5 ~ 3.7 v vddq suppl y volta g e for output with respect to vssq -0.5 ~ 3.7 v vi input volta g e with respect to vss -0.5 ~ vdd+0.5 v vo output volta g e with respect to vssq v io output current 50 ma pd power dissipation ta = 25 c 1000 mw topr operatin g temperature 0 ~ 70 c tst g stora g e temperature -65 ~ 150 c -0.5 ~ vdd+0.5 dc opera ting conditions cap acit ance (ta=0 ~ 70c, unless otherwise noted) symbol parameter test condition limits unit notes min. max. ci(a) input capacitance, address pin vi=1.25v f=100mhz vi=25mvrm 2.5 3.5 pf 11 ci(c) input capacitance, control pin 2.5 3.5 pf 11 ci(k) input capacitance, clk pin 2.5 3.5 pf 11 ci/o i/o capacitance, i/o, dqs, dm pin 4.0 5.0 pf 11 cdi/o data i/o capacitance,i/o,dqs,dm pin - 0.5 pf 11 co(qf) output capacitance, /qfc 2.5 3.5 pf 11 (ta=0 ~ 70 c, unless otherwise noted) symbol parameter limits unit min. typ. max. vdd supply voltage for output v vddq v vih (dc) low-level input voltage vref +0.18 vddq+0.3 v vil (dc) -0.3 vref -0.18 v vref input reference voltage 0.49*vddq 0.51*vddq v vin(dc ) input differential voltage,clk and /clk -0.3 vddq+0.3 v vid(dc ) vddq+0.6 v vtt i/o termination voltage v vref + 0.04 note s 6 5 7 2.3 supply voltage high-level input voltage input voltage,clk and /clk 2.5 -6,-75 -6,-75 -6,-75 2.3 2.5 -6,-75 -6,-75 -6,-75 -6,-75 -6,-75 vref - 0.04 2.7 2.7 0.36
32 integrated silicon solution, inc. ? 1-800-379-4774 rev. a 05/13/05 issi ? is43r83200a -6,-75 (4-bank x 8,388,608 - word x 8-bit) is43r16160a -6,-75 (4-bank x 4,194,304 - word x 16-bit) a verage suppl y current fr om vdd ac opera ting conditions and characteristics
(ta=0 ~ 70c, unless otherwise noted) (ta=0 ~ 70 c, unless otherwise noted) 8 7 ma ma a a v v v v note unit 15.2 -15.2 2 -2 5 -5 0.5*v dd q+0.2 0.5*v dd q-0.2 v dd q + 0.6 0.7 vref -0.35 vref +0.35 max. min. limits output low current (vout=0.35v) output high current (vout=1.95v) input current / vin=0 ~ vddq off-state output current /q floating vo=0~v dd q input crossing point voltage, clk and /clk input differential voltage, clk and /clk low-level input voltage (ac) high-level input voltage (ac) parameter/test conditions i i iol ioh ioz vix(ac) vid(ac) vil(ac) vih(ac) symbol -6,-75 -6,-75 symbol parameter/test conditions organization limits(max.) unit notes -6 -75 idd0 operating current: one bank; active-precharge; t rc = t rc min; t ck = t ck min; dq, dm and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle all 9 5 90 ma idd1 operating current: one bank; active-read-precharge; burst = 2; t rc = t rc min; cl = 2.5; t ck = t ck min; iout= 0ma; address and control inputs changing once per clock cycle x8 12 5 1 15 x16 145 1 3 5 idd2p precharge power-down standby current: all banks idle; power-down mode; cke < vil (max); t ck = t ck min all 6 6 idd2f idle standby current: /cs > vih (min); all banks idle; cke > vih (min); t ck = t ck min; address and other control inputs changing once per clock cycle all 3 5 3 5 idd3p active power-down standby current: one bank active; power-down mode; cke < vil (max); t ck = t ck min all 20 20 idd3n active standby current: /cs > vih (min); cke > vih (min); one bank; active-precharge; t rc = t ras max; t ck = t ck min; dq,dm and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle all 5 0 5 0 idd4r operating current: burst = 2; reads; continuous burst;one bank active; address and control inputs changing once per clock cycle;cl=2.5; t ck = t ck min; iout = 0 ma x8 225 1 7 0 x16 2 45 2 10 idd4w operating current: burst = 2; writes; continuous burst; one bank active; address and control inputs changing once per clock cycle; cl=2.5; t ck = t ck min;dq, dm and dqs inputs changing twice per clock cycle x8 2 10 1 65 x16 2 2 0 20 0 idd5 auto refresh current: t rc = t rfc (min) al l 140 140 idd6 self refresh current: cke < 0.2v all 3 9 3
integrated silicon solution, inc. ? 1-800-379-4774 33 rev. a 05/13/05 issi ? is43r83200a -6,-75 (4-bank x 8,388,608 - word x 8-bit) is43r16160a -6,-75 (4-bank x 4,194,304 - word x 16-bit) ac timing requirements
(ta=0 ~ 70c, unless otherwise noted) 1.75 1.75 sy mb ol ac ch ar act er is ti cs pa ra me te r -6 -75 unit notes min. max. min. max. tac output access time from clk//clk -0.7 0.7 -0.75 0.75 ns td qs ck dq ou tp ut va li d da ta de la y ti me fr om cl k/ /c lk -0.6 0.6 -0.75 0.75 ns tc hc lk hi gh le ve l wi dt h 0.45 0.55 0.45 0.55 tck tc lc lk lo w le ve l wi dt h 0.45 0.55 0.45 0.55 tck th pc lo ck ha lf pe ri od tclmin or tchmin tclmin or tchmin 20 tck clk cycle time cl=3 6 10 7.5 15 ns cl=2.5 6 10 7.5 15 ns cl=2 7.5 15 10 15 ns td s in pu t se tu p ti me (d q, dm ) 0.45 0.5 ns td h in pu t ho ld ti me (dq ,d m) 0.45 0.5 ns th zd at a- ou t- hi gh im pe da nc et im ef ro m cl k/ /c lk -0.7 0.7 -0.75 0.75 ns 14 tlz da ta -o ut -l ow im pe da n ce ti me fr om cl k/ /c lk -0.7 0.7 -0.75 0.75 ns 14 tdqsq dqs-dq skew (for dqs and associated dq signals) 0.45 0.5 ns tdqsqa dqs-dq skew (for dqs and associated dq signals) 0.45 0.5 ns tq ho ut pu t dq s va li d wi nd ow thp-0.55 thp-0.75 ns td qs sw ri te co mm an dt o fi rs t dq s la tc hi ng tra ns it io n 0.75 1.25 0.75 1.25 tck td qs hd qs in pu t hi gh le ve l wi dt h 0.35 0.35 tck td qs ld qs in pu tl ow le ve lw id th 0.35 0.35 tck tm rd mo de re gi st er se t com ma nd cy cl e ti me 12 15 ns tw pr es wr it e pr ea mb le se tu p ti me 0 0 ns 16 tw ps tw ri te po st am bl e 0.4 0.6 0.4 0.6 tck 15 tw pr ew ri te pr eam bl e 0.25 0.25 tck ti si np ut se tu p ti me (a dd re ss an dc on tr ol ) 0.8 0.9 ns 19 ti hi np ut ho ld ti me (a dd re ss an dc on tr ol ) 0.8 0.9 ns 19 tr ps tr ead pos ta mb le 0.4 0.6 0.4 0.6 tck tr pr er ead pr eam bl e 0.9 1.1 0.9 1.1 tck tdss dqs falling edge to clk setup time 0.2 0.2 tck tdsh dqs falling edge hold time from clk 0.2 0.2 tck tdipw dq and dm input puls width (for each input) 1.75 ns 1.75
34 integrated silicon solution, inc. ? 1-800-379-4774 rev. a 05/13/05 issi ? is43r83200a -6,-75 (4-bank x 8,388,608 - word x 8-bit) is43r16160a -6,-75 (4-bank x 4,194,304 - word x 16-bit) ac timing requirements(continous) (ta=0 ~ 70c, unless otherwise noted) ou tpu t load con dit ion dq dqs
v re f v re f v out v re f 30p f 50 ? v tt =v re f zo = 50 ? ou tp ut t i m i ng mea sure m e n t r e fere nce point max. tr as ro w ac ti ve ti me tr cr ow cy cl e ti me (o pe ra ti on ) tr fc au to re f. to ac ti ve /a ut o re f. co mm an dp er io d tr cd ro w to co lu mn de la y tr pr ow pr ec ha rg e ti me t rrd ac t to ac t de la y ti me tw rw ri te re co ve ry ti me tw tr in te rn al wr it et o re ad co mm an dd el ay tr ef ia ve ra ge pe ri od ic re fr es hi nt er va l unit notes sy mb ol ac ch arac te ri st ic sp a ram et er s tck ns ns ns ns ns ns ns -6 -75 min. max. min. 120k 120k 7.8 7.8 txsnr exit self ref. to non-read command txsrd exit self ref. to read command tck ns txpnr exit power down to command txprd exit power down to read command tdal auto precharge write recovery + precharge time ns tck tck 17 18 45 65 75 20 20 15 15 1 75 200 1 1 35 42 60 72 18 18 12 15 1 75 200 1 1 30
integrated silicon solution, inc. ? 1-800-379-4774 35 rev. a 05/13/05 issi ? is43r83200a -6,-75 (4-bank x 8,388,608 - word x 8-bit) is43r16160a -6,-75 (4-bank x 4,194,304 - word x 16-bit) notes: 1 . all voltages referenced to vss. 2. tests for ac timing, idd, and electrical, ac and dc characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. ac timing and idd tests may use a vil to vih swing of up to 1.5v in the test environment, but input timing is still referenced to vref (or to the crossing point for ck//ck), and parameter specifications are guaranteed for the specified ac input levels under normal use conditions. the minimum slew rate for the input signals is 1v/ns in the range between vil(ac) and vih(ac). 4. the ac and dc input level specifications are as defined in the sstl_2 standard (i.e. the receiver will effectively switch as a result of the signal crossing the ac input level, and will remain in that state as long as the signal does not ring back above (below) the dc input low (high) level. 5. vref is expected to be equal to 0.5*vddq of the transmitting device, and to track variations in the dc level of the same. peak-to-peak noise on vref may not exceed +/-2% of the dc value. 6. vtt is not applied directly to the device. vtt is a system supply for signal termination resistors, is expected to be set equal to vref, and must track variations in the dc level of vref. 7. vid is the magnitude of the difference between the input level on clk and the input level on /clk. 8. the value of vix is expected to equal 0.5*vddq of the transmitting device and must track variations in the dc level of the same. 9. enables on-chip refresh and address counters. 10. idd specifications are tested after the device is properly initialized. 11. this parameter is sampled. vddq = +2.5v 0.2v, vdd = +2.5v 0.2v , f = 100 m hz, ta = 25 c, vout(dc) = vddq/2, vout(peak to peak) = 25mv. dm inputs are grouped with i/o pins - reflecting the fact that they are matched in loading (to facilitate trace matching at the board level). 12. the clk//clk input reference level (for timing referenced to clk//clk) is the point at which clk and /clk cross; the input reference level for signals other than clk//clk, is vref. 13. inputs are not recognized as valid until vref stabilizes. exception: during the period before vref stabilizes, cke =< 0.3vddq is recognized as low. 14. t hz and tlz transitions occur in the same access time windows as valid data transitions. these parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (hz), or begins driving (lz). 15. the maximum limit for this parameter is not a device limit. the device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 16. the specific requirement is that dqs be valid (high, low, or at some point on a valid transition) on or before this clk edge. a valid transition is defined as monotonic, and meeting the input slew rate specifications of the device. whe n no writes were previously in progress on the bus, dqs will be transitioning from high-z to logic low. if a previous write was in progress, dqs could be high, low, or transitioning from high to low at this time, depending on tdqss. 17. a maximum of eight auto refresh commands can be posted to any given ddr sdram device. 18. txprd should be 200 tclk in the condition of the unstable clk operation during the power down mode. 19. for command/address and ck & /ck slew rate 1.0v/ns. 20. min (tcl,tch) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device.
36 integrated silicon solution, inc. ? 1-800-379-4774 rev. a 05/13/05 issi ? is43r83200a -6,-75 (4-bank x 8,388,608 - word x 8-bit) is43r16160a -6,-75 (4-bank x 4,194,304 - word x 16-bit) ordering information commercial range: 0c to +70c frequency speed (ns) order part no. organization package 166 mhz 6 is43r83200a-6t 32mx8 66-pin tsop-ii 6 is43r83200a-6tl 32mx8 66-pin tsop-ii, lead-free 6 is43r16160a-6t 16mx16 66-pin tsop-ii 6 is43r16160a-6tl 16mx16 66-pin tsop-ii, lead-free 133 mhz 7.5 is43r83200a-75t 32mx8 66-pin tsop-ii 7.5 is43r83200a-75tl 32mx8 66-pin tsop-ii, lead-free 7.5 IS43R16160A-75T 16mx16 66-pin tsop-ii 7.5 IS43R16160A-75Tl 16mx16 66-pin tsop-ii, lead-free

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